When Elon Musk took the stage at the recent TERAFAB event, the stated goals were nothing short of staggering. By aiming to produce 1 TWh of compute capacity per year, the combined forces of Tesla, SpaceX, and xAI are attempting to capture a massive percentage of Earth's total silicon production output.
However, industry analysts immediately pointed to the elephant in the room: ASML. The Dutch company holds an absolute monopoly on the Extreme Ultraviolet (EUV) lithography machines required to print leading-edge chips, and its order book is already backed up for years. You cannot simply order a fleet of High-NA EUV machines and expect them to be delivered next year.
So, how does Musk plan to build the world’s largest AI hardware operation while bypassing the biggest supply chain bottleneck in the technology sector? The answer lies in a newly formed alliance with Intel, a shift toward Gallium Nitride, and a fundamental rethinking of how AI chips are packaged.
ASML and Modern Chips
To understand the magnitude of this strategy, it is important to understand why ASML is the ultimate chokepoint for global semiconductor production. The Netherlands-based company is the world's only manufacturer of Extreme Ultraviolet (EUV) lithography machines. These massive, highly complex devices use incredibly short wavelengths of light to print microscopic, intricate circuit patterns onto silicon wafers.
If a tech company wants to build the most advanced logic chips on the market, pushing down to incredibly dense 3nm or 2nm nodes, they absolutely must use ASML's EUV technology. Because ASML is the sole supplier, and because each machine takes months to build and calibrate, its order book is perpetually backlogged. For a massive new project like TERAFAB to hit the ground running, waiting years for a fleet of EUV machines simply is not an option.
The GaN Chiplet Pathway
The most critical piece of the puzzle is the recently announced partnership between Tesla, SpaceX, and Intel. Just as this deal was inked, Intel announced a major breakthrough in Gallium Nitride (GaN) chiplet architecture. This is not a coincidence.
Intel Foundry unveils the world’s thinnest GaN chiplet (19 μm).
— Intel Foundry (@Intel_Foundry) April 8, 2026
By integrating power and digital control on a single chiplet, it delivers higher efficiency, faster switching, and smaller designs.
Learn more: https://t.co/EvI9UVxktY#IntelFoundry #Semiconductors pic.twitter.com/mEmIWHbXZx
Traditional silicon logic chips rely on endless miniaturization, shrinking down to 3nm and 2nm nodes to increase transistor density and power efficiency. That specific shrinking process requires ASML's most advanced, heavily backlogged EUV machinery. GaN operates under a different set of physical rules. It can handle significantly higher voltages, temperatures, and frequencies than silicon.
Because of these inherent material advantages, highly efficient GaN chiplets can be manufactured on slightly more mature nodes using widely available Deep Ultraviolet (DUV) lithography equipment. By leaning heavily into GaN architectures, TERAFAB can sidestep the queue for ASML's bleeding-edge machines while still achieving massive leaps in power efficiency.
Radiation Tolerance and Space-Based Compute
The pivot to GaN solves more than just a supply chain issue. It directly serves the needs of SpaceX. Silicon is highly susceptible to radiation, which is why deploying advanced neural networks in space has traditionally required bulky, expensive physical shielding.
GaN is inherently radiation-tolerant. By shifting the core architecture to GaN chiplets, TERAFAB is effectively building off-the-shelf, space-ready hardware. This perfectly aligns with Musk's broader vision of deploying massive, solar-powered xAI data centers in low Earth orbit via Starship, allowing the network to scale without draining the terrestrial power grid.
Advanced Packaging Over Node Shrink
Another key strategy to bypass the ASML bottleneck is TERAFAB’s commitment to "full packages," which includes integrating NAND memory directly alongside the compute cores.
Instead of trying to print one massive, flawless monolithic chip on a backlogged 2nm node, TERAFAB is utilizing advanced 3D packaging. This allows them to print smaller, specialized chiplets on mature nodes and stitch them together using Intel's advanced packaging technologies, such as Foveros or glass substrates.
By bringing the logic, power delivery, and NAND memory into a single, tightly integrated package, the data transfer speeds between the components increase exponentially.
This approach uses packaging engineering to achieve performance gains that the rest of the industry is trying to achieve through lithography shrinking.
Brute Force and Vertical Integration
Finally, TERAFAB’s strategy relies on raw scale. Companies like Nvidia and Apple fight for ASML capacity because their chips must fit inside server racks with strict thermal limits or mobile phones with tiny batteries.
Musk's approach is entirely vertically integrated. Tesla and xAI control the power generation, the cooling systems, the server racks, and the software compiler. If a TERAFAB chip is slightly larger because it was printed on a mature node rather than an ASML EUV machine, it does not matter. They simply build a larger server rack, power it with Tesla Megapacks, and cool it with specialized liquid loops.
By leveraging Intel's GaN breakthroughs, advanced 3D packaging, and a willingness to solve compute problems with brute-force infrastructure, Musk has charted a viable path to 1 TWh of compute that completely circumvents the ASML waiting list.
